Position OverviewWe are looking for someone with strong technical, analytical and problem-solving skills, as well as demonstrating the characteristics of an independent and resourceful individual. The applicant must have a proficient understanding of semiconductor fabrication, testing or relevant industry processes, and experience in product/process engineering, semiconductors, or relevant manufacturing with ATE test platforms.
KEY RESPONSIBILITIES:Drive initiatives for final test yield enhancement, cycle time reduction, and quality improvement.Support daily engineering debug activities.Generate, organize and maintain documentation for product manufacturability.Support lot-on-hold disposition based on sound technical judgement.Produce yield and pareto reports per requirements.Coordinate with internal Operations Team and External Subcons to facilitate testing and shipment of both NPI and Sustaining devices.
PREFERRED EXPERIENCE:At least 2-5 years of experience in ATE Test patterns, flows, debug, and experience working in Product Engineering team.Hands-on experience in ATE Test handling/execution and data analysis - Advantest T2K experience preferred (Advantest V93K experience is a plus).Experience in Scan, MBISTSoftware programming and scripting proficiency (C++, Python).Strong and effective presentation, written and verbal communication skills.Excellent interpersonal, organizational, and analytical skills.
ACADEMIC CREDENTIALS:Degree in Electrical/Electronics Engineering, or comparable disciplines.
THE ROLE:If you are looking for a fulfilling and challenging career as an engineer leading SLT (System Level Test) IVR (Integrated Voltage Regulator) Engineer, you are at the right place! In this role, you will be responsible for defining, driving and enabling SLT test solution with on-chip integrated voltage regulator to meet NPI business milestones and KPI (test time, yield, cost, quality).The expectation is to perform leadership to interact with Silicon/Board/Power design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to bring new product from first silicon to HVM (High Volume Manufacturing) with aggressive schedule.
THE PERSON:We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual. The applicant must have a proficient understanding of High Power Delivery (above 1kW) design, power capacitors and inductors, buck/boost converters, and ideally has experience with IVR (Integrated Voltage Regulator) as well as a broad understanding of silicon VFT (Voltage/Frequency/Temperature) behavior, on-die silicon power integrity, and system level power management etc.
KEY RESPONSIBILITIES:Accountable to provide leadership to meet business milestone, cost and quality in GPU system level test area.Collaborate with internal teams to drive IVR (Integrated Voltage Regulator) SLT swim lane from pre-silicon, ASIC initial bring up to HVM (High Volume Manufacturing).Solves complex, novel, and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation.Conduct engineering evaluations and analysis to qualify cutting-edge IVR for HVM and drive closure of GPU production issues.Profile or characterize PI (Power Integrity), voltage droop, or power delivery issue observed on SLT platforms in collaboration with board/silicon designers.Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives.May provide technical supervision or mentoring junior engineers.Upscale overall team capabilities on low level system debug.
PREFERRED EXPERIENCE:8 years or more industry experience.Experience and with good understanding of Power Delivery design for high power GPU product (above 1kW), and knowledge in state-of-the-art of IVR (Integrated Voltage Regulator).Strong expertise with using analyzers and oscilloscopes, and other debug tools.Knowledge and working experience on GPU and HBM architecture, SoC design and SoC power management features are a strong plus.Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams.Proficiency in Windows, and Linux operating systems.Basic scripting proficiency for automation (Shell script, Perl, Ruby, Python).
ACADEMIC CREDENTIALS:· BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines
We are seeking an ATE Test Engineer to develop and validate test programs for CPU/GPU products and IPs, supporting the full product lifecycle from characterization to post-manufacturing.
Education & Experience:Degree in Electrical & Electronics Engineering.5-8 years of relevant experience, preferably with CPU/GPU products or IPs.Experience with Test IPs (Scan, MBIST, Functional, Analog-Mixed Signals, High-Speed I/O) and DFT concepts.Experience in OSAT qualification, manufacturing support, and statistical data analysis.
Technical Skills:Test development on Verigy 93K (Mandatory), including flow design, pattern/debug, and failure analysis.Hands-on experience with ATE testers and handlers.Proficiency in Unix/Windows and scripting (Java, Perl, Python)Possess experience in IPs in most/all the IPs such as DDR, PLL, IOSPEC, Display, USB, PCIE, etc.Strong understanding of digital testing concepts.Bonus experience in Scan, MBIST, HSIO, Functional, JTAG, SIDD, or IOSpec tests.
Key Responsibilities:Plan and execute pattern bring-up, characterization, HTOL, and package qualification.Develop, validate, and release ATE test programs; align test points and define VID bucketing.Collaborate with Package, HWI, and design teams for hardware and content readiness.Plan and execute sample deliveries, yield attainment, and test time optimization.Support RMA debug and drive quality improvements to meet target DPPM.Support manufacturing and post-manufacturing product lifecycle activities.
Soft Skills:Strong problem-solving, communication, and teamwork skills.Self-motivated and independent, with excellent interpersonal abilities.
THE ROLE:Test Engineering is a cost, quality, and time-to-market driven team responsible for enabling the availability of graphic products.Pre-silicon responsibilities for the Test Engineer include understanding product features, development of test plans and requirements, and developing software and hardware infrastructure to execute those plans. This requires interaction with Design and Platform Engineering and allows for the opportunity to provide test enhancement feedback for future designs.Post-silicon responsibilities include on time delivery of tests coverage and the execution of characterization plans. This may include debugging of silicon test performance issues, yield issues, manufacturing processes, and device marginalities. The Test Engineer will work closely with Design and Platform Engineering to root cause issues that result from the debug, characterization and margin analysis.
THE PERSON:Position involves test program development, characterization, data analysis, and silicon debug, preferably with experience in area of Test Program, Fuse and characterization program generation, hardware DIB design requirements, and support of IP level tests bring up in leading edge process technologies.
KEY RESPONSIBILITIES:Test patterns & test flows development, debug, test and characterization.Experience skillsets include ATE Test Program development 93K, PBI (Post Burn-in) test program, ATE test methodologies development, DIB design, Fuse module tests, Thermal module tests.Characterization and debug of new silicon designs and process technologies.Optimization of test coverage and flows for increased quality, yield, cost improvement, and test time reduction.Analysis of part failures leading to test coverage improvement.Analysis of characterization data.
PREFERRED EXPERIENCE:5 years or more industry experience.Good communication skills including data analysis and presentation.Unix and Windows proficiency and Java, Perl, Python scripting skills.ATE Test handling/ execution and development experience - Advantest V93K experience preferred.Some IP knowledge, development and debug experience will be advantage.
ACADEMIC CREDENTIALS:· BS/MS EE or equivalent
