About the role:
This role focuses on silicon characterization, test program correlation, and high-volume production release support for new semiconductor designs. You will collaborate closely with design, validation, and architecture teams to ensure complete test coverage, meet qualification timelines, and achieve yield and quality targets. You will also drive test time reduction, cost optimization, and continuous quality improvement initiatives.
KEY RESPONSIBILITIES:Collaborate with IP design, validation, and architecture teams for test content coverage, characterization planning, and qualification timeline alignment.Characterize new silicon designs and process technologies.Analyze test program correlation data before release for high volume production.Drive yield and quality goals; Identify test, yield, and quality improvement opportunities.Support cost reduction analyses for test time reduction or test removal.
PREFERRED EXPERIENCE:Proficient experience with data analysis tools such as JMP or Jupyter.Familiar with concepts surrounding wafer fabrication processes.Demonstrated experience in statistical analysis.Proficient in software programming and scripting languages. (SQL, C, C++, Java, Ruby, Perl, Python)Proficient in Windows, Unix, and Linux operating systems.Knowledgeable in modern computer architecture and semiconductor device physics.Hands-on experience with Scan and BIST architectures.
Responsibilities:Collaborate with design, validation, and architecture teams for IP content coverage, test pattern and test program development, validation, and debug.Develop test program infrastructure incorporating latest Best-Known Methods.Validate new product features, test conditions, test methodologies, and test contents during first silicon bring-up.Perform silicon characterization across process, voltage, and temperature.Perform test program correlation and release for high volume production.Drive Key Performance Indicators such as test time reduction, yield debug, and quality improvement across products.Support qualification activities and customer return debug.
Requirements:At least 4 years of experience in semiconductor product development.Experience with ATE test program and pattern development – Advantest 93K, a must.DFT/Scan and test program integrations experiences.Proficient in software programming and scripting languages (C, C++, Java, Ruby, Perl, Python).Knowledgeable in version control tools (Git, SVN, CVS).Knowledgeable in statistical analysis.Proficient in Windows, Unix, and Linux operating systems.Strong written and verbal communication skills.
Job Title: AMS / HSIO Test Engineer (V93K)Job OverviewWe are looking for an experienced AMS / HSIO Test Engineer with hands-on experience in high-speed interface validation and ATE testing.Candidate should have working experience in one or more of the following modules:DDR (Preferred)DisplayUSBPCIePLLIOSPECExperience on Advantest V93K (93K) tester is required.
Key ResponsibilitiesDevelop, debug, and maintain test programs on Advantest V93KPerform silicon validation and characterization for AMS / HSIO modulesDebug test failures and support yield improvement activitiesWork closely with design, validation, and product engineering teamsSupport production bring-up and manufacturing testing
RequirementsDegree in Electrical / Electronics Engineering or related fieldHands-on experience with Advantest V93K testerExperience in at least one HSIO domain (DDR / PCIe / USB / Display / PLL / IOSPEC)Experience in semiconductor test or validation environmentStrong debugging and analytical skills
PreferredDDR testing experienceAMS / mixed-signal validation experienceAutomation or scripting knowledge is a plus
JD: Product Development Engineer/Test (ATE)Responsibilities:Collaborate with design, validation, and architecture teams for IP content coverage, test pattern and test program development, validation, and debugDevelop test program infrastructure incorporating latest Best-Known MethodsValidate new product features, test conditions, test methodologies, and test contents during first silicon bring-upPerform silicon characterization across process, voltage, and temperaturePerform test program correlation and release for high volume productionDrive Key Performance Indicators such as test time reduction, yield debug, and quality improvement across productsSupport qualification activities and customer return debugRequirements:More than 4 years of experience in semiconductor product developmentExperience with ATE test program and pattern development – Advantest 93K, a must.DFT/Scan and test program integrations experiences.Proficient in software programming and scripting languages (C, C++, Java, Ruby, Perl, Python)Knowledgeable in version control tools (Git, SVN, CVS)Knowledgeable in statistical analysisProficient in Windows, Unix, and Linux operating systemsStrong written and verbal communication skills
🚀 AMS / HSIO Test Engineer (Advantest V93K) – Singapore (Onsite)📍 Location: Singapore 🌏 Open to: Malaysia-based candidates willing to relocate，local candidates🔍 About the RoleWe are looking for an experienced AMS / HSIO Test Engineer to join a high-impact semiconductor project.This role focuses on high-speed interface validation and ATE testing, supporting advanced silicon bring-up and production.💡 Key ResponsibilitiesDevelop, debug, and maintain test programs on Advantest V93K (93K SMT7/8)Perform silicon validation & characterization for AMS / HSIO modulesAnalyze test failures and drive yield improvementCollaborate with Design, Validation & Product Engineering teamsSupport production bring-up & manufacturing testingParticipate in pre-silicon planning, including:Test plan definitionLoadboard schematic review🧠 RequirementsBachelor’s degree in Electrical / Electronics Engineering or related field5+ years hands-on experience with Advantest V93K testerExperience in at least ONE HSIO domain:DDR (highly preferred)PCIe / USB / Display / PLL / IOSPECStrong debugging and problem-solving skillsBackground in semiconductor testing / validation⭐ Preferred QualificationsExperience in DDR testingExposure to AMS / mixed-signal validationKnowledge of automation / scripting (Python, etc.)🌟 Why Join This Opportunity?Work on cutting-edge semiconductor technologiesExposure to global engineering teamsOpportunity to contribute to high-performance chip developmentStrong career growth in ATE & HSIO domain📩 Interested?Feel free to apply or reach out directly for more details!
📌 SoC / FPGA Characterization EngineerLocation: Singapore Company: ThunderSoft (Leading Semiconductor Client) Type: Full-time, On-site🔍 About the RoleWe are looking for a Characterization Engineer to join our team in Penang, supporting performance evaluation of advanced Adaptive SoC and FPGA products.In this role, you will work on pre- and post-silicon validation, focusing on performance, timing, voltage, and silicon behavior across operating conditions. This is a great opportunity to work on cutting-edge semiconductor technologies in a collaborative and innovation-driven environment.🛠 Key ResponsibilitiesDevelop, execute, and debug characterization test suites (hardware & software)Evaluate performance, timing, frequency, and voltage margins of SoC/FPGA subsystemsMaintain and port test patterns, automation scripts, and validation flows across platforms (including ATE)Analyze silicon data across different operating conditions and generate characterization reportsIdentify trends, debug issues, and collaborate with cross-functional teams (design, validation, etc.)✅ Requirements (Must-have)Bachelor’s degree in Electrical Engineering / Computer Engineering / Computer Science or related field5+ years of experience in pre- or post-silicon validation / characterizationExperience with SoC or FPGA validationStrong skills in debugging and performance analysisProficiency in at least one scripting language (Python / Tcl / Perl)Programming skills in C/C++⭐ Nice to HaveExperience with ATE (Automated Test Equipment)Knowledge of VHDL / Verilog / SystemVerilogUnderstanding of EDA tools and design flowsFamiliarity with embedded processor systems and interconnectsBasic knowledge of statistical data analysis💡 Why JoinWork with a leading global semiconductor clientExposure to advanced SoC / FPGA technologiesStrong technical growth in validation and silicon engineeringCollaborative and innovation-driven team environment
Key ResponsibilitiesDevelop, debug, and maintain test programs on Advantest V93K.Perform silicon validation and characterization for AMS / HSIO modules.Debug test failures and support yield improvement activities.Work closely with design, validation, and product engineering teams.Support production bring-up and manufacturing testing.Pre-silicon planning, including test list review with Design and Loadboard schematic review.
RequirementsDegree in Electrical / Electronics Engineering or related field.5 years hands-on experience with Advantest V93K tester.Experience in at least one HSIO domain (DDR / PCIe / USB / Display / PLL / IOSPEC).Experience in semiconductor test or validation environment.Strong debugging and analytical skills.
PreferredDDR testing experience.AMS / mixed-signal validation experience.Automation or scripting knowledge is a plus.
Job DescriptionTHE ROLE:As a New Product Introduction Engineer, you will drive product cost through Yield improvement, quality with test content and test points design, and product definition/bounding box development. You will work closely with world class Product Test, Design, Quality, Reliability, Customer, Software and Platform global teams to plan and develop the final product solution to meet KPI targets. With close collaboration with end customer, you will also have insights into the product and guide your team to achieve customer expectations
We are the high-end test engineering team providing test solutions for Data Center Graphics (DCG) New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, enterprise servers, and Artificial Intelligence clusters.
If you are looking for a fulfilling and challenging career as an engineer leading NPI ATE Product Development, you are at the right place! As a (Senior) MTS Product Development Engineer, you will be responsible for developing and driving ATE test solution to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership through interaction with design teams, Product & Test Engineering teams, Quality & Reliability teams, software & platform teams to come up with the best solution that balance quality and cost. You will experience working with and learning from AMD’s talented engineering teams around the world.
THE PERSON:We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual. Preferably, the candidate should have high understanding of product development ecosystem. The candidate should possess good communication skills as this is the key to successful collaboration.
The applicant must have a strong background in Integrated Voltage Regulator (IVR) testing and characterization, with hands-on expertise in Teradyne or Advantest ATE platforms. In this role, you will be responsible for developing and executing test solutions for IVRs used in advanced SoC and power management applications. You will work closely with design, product, and validation teams to ensure robust test coverage, yield optimization, and reliable product performance.
KEY RESPONSIBILITIES:Lead engineering efforts in silicon characterization and analysis to define products that meet customer requirements, yield, and cost targets.Provide technical leadership across PEO teams, aligning design feedback, customer requirements, and product goals.Represent PEO in design discussions, influencing decisions that significantly impact final product outcomes.Conduct gate reviews for test, cost, and quality at key development milestones.Drive timely resolution of customer-reported issues in collaboration with quality and support teams.Develop ATE test programs and hardware (e.g., load boards, probe cards) for validation, characterization, and production testing of IVRs.Utilize platforms such as Teradyne (UltraFlex, J750) and Advantest (V93000, T2000) to implement and debug analog/mixed-signal test routines.Support test development from pre-silicon through high-volume manufacturing, including PVT characterization and detailed reporting.Perform power-related testing (e.g., PSRR, efficiency, transient response) and stability analysis.Collaborate with design and systems teams to define test specifications and translate design intent into executable test plans.Automate data collection and analysis using tools like Python, MATLAB, or JMP.Lead root-cause analysis of silicon issues using both ATE and bench-level tools.Drive initiatives for test time reduction, yield enhancement, and cost optimization.
PREFERRED EXPERIENCE:Over 7 years of experience in the semiconductor industry, with a strong foundation in analog/mixed-signal IC testing and ATE development.Skilled in data extraction, manipulation, and visualization using statistical tools such as correlation analysis, predictive modeling, contrast analysis, and machine learning.Proficient in wafer, final test (FT), and system-level test (SLT) methodologies and equipment.Solid understanding of Design of Experiments (DOE), failure analysis, and RMA processes.Background in solid-state physics, computer architecture, and both digital and analog design.Experienced in Python for data analysis, SQL for database queries, and scripting in C, C++, Java, Ruby, and Perl.Strong command of Excel, JMP, Yield Explorer, SAS, Power BI, and other EDA tools.Comfortable working across Windows and Unix/Linux environments.Proven ability to manage multiple projects under tight deadlines with strong communication and organizational skills.Hands-on experience with on-die and integrated voltage regulators in advanced CMOS nodes.Familiar with high-volume manufacturing, test correlation between ATE and bench, and reliability qualification (ESD/Latch-up, HTOL).Knowledgeable in test hardware design and debugging (probe cards, load boards), and test cost optimization techniques.Proficient in developing/debugging test programs on Teradyne and Advantest ATE platforms.Strong grasp of power management circuits including buck/boost converters, LDOs, and SVI3/I2C/I3C protocols.Experienced with lab instrumentation such as oscilloscopes, SMUs, electronic loads, and network analyzers.Skilled in silicon bring-up, PVT characterization, and yield analysis with robust troubleshooting capabilities
ACADEMIC CREDENTIALS:BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines
LOCATION:Singapore
Product Development Engineer/Test (ATE)
THE PERSON: Position involves test program development, characterization, data analysis, and silicon debug, preferably with experience in area of Test Program, Fuse and characterization program generation, hardware DIB design requirements, and support of IP level tests bring up in leading edge process technologies.
KEY RESPONSIBILITIES: • Test patterns & test flows development, debug, test and characterization• Experience skillsets include ATE Test Program development on Advantest 93K• Characterization and debug of new silicon designs and process technologies• Optimization of test coverage and flows for increased quality, yield, cost improvement,and test time reduction• Analysis of part failures leading to test coverage improvement• Analysis of characterization dataPREFERRED EXPERIENCE: • Good communication skills including data analysis and presentation• Unix and Windows proficiency and Java, Perl, Python scripting skills• ATE Test handling/ execution and development experience - Advantest V93K Smartest8 experience preferred.• Some IP knowledge, development and debug experience will be advantageWORKING HOURS: • Permanent night shift.ACADEMIC CREDENTIALS: • BS/MS EE or equivalent
Job DescriptionTHE ROLE:We are the high-end test engineering team providing test solutions for Data Center New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, and enterprise servers. If you are looking for a fulfilling and challenging career as an engineer leading SLT (System Level Test) IVR (Integrated Voltage Regulator) Engineer, you are at the right place! In this role, you will be responsible for defining, driving and enabling SLT test solution with on-chip integrated voltage regulator to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership to interact with Silicon/Board/Power design teams, Product & Test Engineering teams, Customer Quality teams, software & platform teams to bring new product from first silicon to HVM (High Volume Manufacturing) with aggressive schedule. You will experience working with and learning from AMD’s talented engineering teams around the world. THE PERSON:We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual. The applicant must have a proficient understanding of High Power Delivery (above 1kW) design, power capacitors and inductors, buck/boost converters, and ideally has experience with IVR (Integrated Voltage Regulator) as well as a broad understanding of silicon VFT (Voltage/Frequency/Temperature) behavior, on-die silicon power integrity, and system level power management etc. KEY RESPONSIBILITIES:Accountable to provide leadership to meet business milestone, cost and quality in GPU system level test area.Collaborate with internal teams to drive IVR (Integrated Voltage Regulator) SLT swim lane from pre-silicon, ASIC initial bring up to HVM (High Volume Manufacturing)Solves complex, novel, and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementationConduct engineering evaluations and analysis to qualify cutting-edge IVR for HVM and drive closure of GPU production issuesProfile or characterize PI (Power Integrity), voltage droop, or power delivery issue observed on SLT platforms in collaboration with board/silicon designersInvolves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiativesMay provide technical supervision or mentoring junior engineersUpscale overall team capabilities on low level system debug for data center product families PREFERRED EXPERIENCE:Experience and with good understanding of Power Delivery design for high power GPU product (above 1kW), and knowledge in state-of-the-art of IVR (Integrated Voltage Regulator)Strong expertise with using analyzers and oscilloscopes, and other debug toolsKnowledge and working experience on GPU and HBM architecture, SoC design and SoC power management features are a strong plusStrong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teamsProficiency in Windows, and Linux operating systemsBasic scripting proficiency for automation (Shell script, Perl, Ruby, Python)8 years or more industry experience
