Job Responsibilities
Design, verify, and optimize CPU microarchitecture to meet instruction set architecture (ISA) functional and performance requirements.Design processor datapaths, control logic, and memory hierarchy.Research and apply advanced techniques—such as superscalar execution, multithreading, branch prediction, out-of-order execution, and multi-level caches—to improve processor performance and efficiency.Work closely with other hardware engineers, software engineers, and verification engineers to ensure thorough validation of CPU functionality and performance.Write and maintain CPU design documentation, including specifications, functional descriptions, and microarchitecture manuals, to support hardware and software development teams.Design multi-core and heterogeneous processor architectures.
Qualifications
Bachelor’s degree or above in Computer Engineering, Electrical Engineering, Microelectronics, or related fields.Preferably 5 years of CPU design experience, with solid knowledge of processor architecture, microarchitecture, datapath design, control logic, and memory hierarchy.Familiarity with the C910 instruction set and related processor architectures; prior experience designing processors based on this architecture is a plus.Proficiency in hardware description languages such as Verilog or VHDL, with strong logical design and engineering implementation skills.Solid understanding of computer architecture and operating system principles, and knowledge of processor performance and efficiency optimization techniques.Strong teamwork skills, good communication and organizational abilities, and good English reading and writing skills, with the ability to read and write technical documentation and reports.
Preferred Qualifications
Experience with performance modeling, simulation, and verification; familiarity with computer architecture and performance analysis tools.Experience in RISC-V processor architecture design.Experience in CPU microcode design and optimization.Experience in CPU power management and power optimization.Experience in implementing CPU security and cryptography technologies.
Job ResponsibilitiesResponsible for ISP algorithm code development, including development and optimization of algorithms such as 3A, noise reduction, and HDR.Develop ISP algorithms and drivers, and create ISP debugging tools.Participate in ISP design and performance optimization for various application scenarios.Provide post-launch technical support for relevant algorithms in products.Responsible for establishing image quality evaluation metrics and testing standards.Job RequirementsBachelor's degree or above in Computer Science, Electronic Engineering, Image Processing, or related fields.Solid foundation in digital image processing theory, with 3+ years of ISP algorithm development experience.Familiar with Linux Camera architecture, including V4L2 and Media Controller.Proficient in the full Camera ISP algorithm workflow, with experience in ISP pipeline and 3A algorithm porting and development; extensive image signal processing experience.Familiar with RAW image analysis tools such as Imatest, with the ability to accurately assess image data quality.Strong programming skills with proficiency in C/C++ or Matlab.
We are looking for a talented Digital IC Design Engineer (SoC) to join our growing team in Singapore. In this role, you will be involved to develop the next-generation AI chips based on a revolutionary architecture. You will work closely with verification, front-end, and software teams to deliver high-quality digital IC solutions.
Key Responsibilities:Micro-architecture & RTL development for AI compute subsystems.Analyze performance, power, and area (PPA) to deliver high-performance compute within strict cost and energy budgets.Contribute to RTL design of SoC modules and assist in IP core integration.Support chip-level system design tasks, including clock/reset architecture, low-power design techniques, and bus architecture.Collaborate with verification and testing teams to perform module-level and system-level validation.Assist front-end engineers in netlist delivery and help resolve timing issues.Provide support for driver development, debugging, and technical documentation.
Requirements:Bachelor’s degree or higher in Electrical Engineering (or equivalent).5 years or above of relevant experience in digital IC/ASIC design.Strong understanding of digital circuit fundamentals and proficiency in Verilog HDL.Familiarity with ASIC design flow and EDA tools (e.g., Synopsys, Cadence).Good understanding of CPU and Cache architectures, instruction set architectures (ISA), and compiler principles.Knowledge of bus systems, DMA, and peripheral interface design.Awareness of low-power design methodologies.
Preferred Qualifications:Familiarity with standard bus protocols (e.g., AMBA, AXI, AHB, APB).Exposure to synthesis, timing analysis, or DFT concepts.Good problem-solving skills and eagerness to learn in a collaborative environment.Strong communication skills and ability to document technical work clearly.
Espressif Systems is hiring an Analog Design Engineer with solid experience in high-speed SerDes PHY design, who can contribute to and own key analog blocks from architecture through silicon.
RequirementsDesign and develop high speed analog and mixed-signal circuits for SerDes PHY.Participate in RX and/or TX circuit design, such as: High speed TX drivers, RX Equalization circuits(e.g. CTLE, DFE),Clocking and data recovery circuits (CDR), High-speed front-end and data path blocksContribute to PHY architecture definition and design trade-offsPerform circuit-level design, simulation, and verification across PVT cornersWork closely with layout engineers to ensure robust high-speed analog layoutSupport silicon bring-up, lab debug, and characterizationCollaborate with digital, system, and packaging teams to ensure end-to-end PHY performanceContribute to in house PHY development and evolution
QualificationsBachelor’s / Master’s / PhD in Electrical Engineering or related field3+ years of work experience in analog or mixed-signal IC designHands-on experience with SerDes, USB/Ethernet/PCIe PHY, or other high-speed interface designsSolid understanding of: High-speed signaling fundamentals, Jitter, noise, and channel effects, Circuit design and verification methodologiesExperience taking designs from concept through tape-out and silicon bring-up is a plusFamiliarity with advanced CMOS technologies, especially FINFET process.Strong problem-solving skills and ability to work in cross-functional teams
We are looking for a highly capable AI Engineer to drive Espressif’s digital transformation initiatives. In this role, you will work closely with different business units to understand their workflows, identify bottlenecks, and build internal systems that significantly improve efficiency. You will design and deliver automation tools, data workflows, and business applications, while actively integrating advanced AI technologies into our internal platforms.
Job Responsibilities
Design, develop, and maintain the automation system for our company's various departments using Python and AICollaborate with departments to explore workflow improvement needs and implement AI-enabled solutions using cutting-edge AI technologies or or LLM modelsDevelop and deploy codebase, automated solutions, and data processing workflows using Python and related technologiesEnhance existing codebase, refactor, debug, and troubleshoot codebase bugsRegularly document work to ensure that it is clear, understandable and informativeStay up-to-date with new trends, techniques, and technologies in AI
Job Requirements
Bachelor's or Master's degree in Computer Science, Computer Engineering, or related fieldsStrong experience in Python and interest in Al agents or chatbot developmentExperience in developing and maintaining complex internal systemsKnowledge of databases and object-relational mapping (ORM)Strong analytical thinking and problem-framing capabilities
