We are looking for a Senior Design Verification Engineer to work on Espressif's next-generation wireless and AI-capable SoCs. You will work closely with RTL designers and chip architects, and provide technical leadership within a small verification sub-team.
Job ResponsibilitiesDefine verification plans and test cases based on design specifications, and own the verification environment end-to-endCollaborate with design engineers to identify and resolve design defects, and continuously drive verification coverage improvementMaintain simulation/verification environments using industry-standard EDA toolsWrite scripts to automate testing workflows in Python, Perl, TCL, or ShellTrack and report code/functional coverage metrics; identify and close gaps before tapeoutDebug failures and root-cause issues, working closely with designers to resolve issuesLeverage AI tools to optimize verification flows and improve team-wide efficiencyMentor junior verification engineers and provide technical guidance across the team
Job RequirementsBachelor's degree or above in Electronic Engineering, Computer Engineering, Computer Science, or a related fieldPreferably 3+ years of ASIC/SoC/IP design verification experienceProficiency in Verilog, SystemVerilog, UVM, and CProficiency in scripting languages such as Python, Perl, Shell, or TCLStrong interest in exploring and adopting AI tools to improve day-to-day engineering productivity and verification efficiency
Job ResponsibilitiesResponsible for ISP algorithm code development, including development and optimization of algorithms such as 3A, noise reduction, and HDR.Develop ISP algorithms and drivers, and create ISP debugging tools.Participate in ISP design and performance optimization for various application scenarios.Provide post-launch technical support for relevant algorithms in products.Responsible for establishing image quality evaluation metrics and testing standards.Job RequirementsBachelor's degree or above in Computer Science, Electronic Engineering, Image Processing, or related fields.Solid foundation in digital image processing theory, with 3+ years of ISP algorithm development experience.Familiar with Linux Camera architecture, including V4L2 and Media Controller.Proficient in the full Camera ISP algorithm workflow, with experience in ISP pipeline and 3A algorithm porting and development; extensive image signal processing experience.Familiar with RAW image analysis tools such as Imatest, with the ability to accurately assess image data quality.Strong programming skills with proficiency in C/C++ or Matlab.
Job Responsibilities
Design, verify, and optimize CPU microarchitecture to meet instruction set architecture (ISA) functional and performance requirements.Design processor datapaths, control logic, and memory hierarchy.Research and apply advanced techniques—such as superscalar execution, multithreading, branch prediction, out-of-order execution, and multi-level caches—to improve processor performance and efficiency.Work closely with other hardware engineers, software engineers, and verification engineers to ensure thorough validation of CPU functionality and performance.Write and maintain CPU design documentation, including specifications, functional descriptions, and microarchitecture manuals, to support hardware and software development teams.Design multi-core and heterogeneous processor architectures.
Qualifications
Bachelor’s degree or above in Computer Engineering, Electrical Engineering, Microelectronics, or related fields.Preferably 5 years of CPU design experience, with solid knowledge of processor architecture, microarchitecture, datapath design, control logic, and memory hierarchy.Familiarity with the C910 instruction set and related processor architectures; prior experience designing processors based on this architecture is a plus.Proficiency in hardware description languages such as Verilog or VHDL, with strong logical design and engineering implementation skills.Solid understanding of computer architecture and operating system principles, and knowledge of processor performance and efficiency optimization techniques.Strong teamwork skills, good communication and organizational abilities, and good English reading and writing skills, with the ability to read and write technical documentation and reports.
Preferred Qualifications
Experience with performance modeling, simulation, and verification; familiarity with computer architecture and performance analysis tools.Experience in RISC-V processor architecture design.Experience in CPU microcode design and optimization.Experience in CPU power management and power optimization.Experience in implementing CPU security and cryptography technologies.
We are looking for a talented Senior ASIC Design Engineer to join our growing team in Singapore. In this role, you will be involved to develop the next-generation AI chips based on a revolutionary architecture. You will work closely with verification, front-end, and software teams to deliver high-quality digital IC solutions.
Key Responsibilities:Micro-architecture & RTL development for AI compute subsystems.Analyze performance, power, and area (PPA) to deliver high-performance compute within strict cost and energy budgets.Contribute to RTL design of SoC modules and assist in IP core integration.Support chip-level system design tasks, including clock/reset architecture, low-power design techniques, and bus architecture.Collaborate with verification and testing teams to perform module-level and system-level validation.Assist front-end engineers in netlist delivery and help resolve timing issues.Provide support for driver development, debugging, and technical documentation.
Requirements:Bachelor’s degree or higher in Electrical Engineering (or equivalent).5 years or above of relevant experience in digital IC/ASIC design.Strong understanding of digital circuit fundamentals and proficiency in Verilog HDL.Familiarity with ASIC design flow and EDA tools (e.g., Synopsys, Cadence).Good understanding of CPU and Cache architectures, instruction set architectures (ISA), and compiler principles.Knowledge of bus systems, DMA, and peripheral interface design.Awareness of low-power design methodologies.
Preferred Qualifications:Familiarity with standard bus protocols (e.g., AMBA, AXI, AHB, APB).Exposure to synthesis, timing analysis, or DFT concepts.Good problem-solving skills and eagerness to learn in a collaborative environment.Strong communication skills and ability to document technical work clearly.
We are looking for a Principal SoC Design Engineer to lead the architecture and design of Espressif's next-generation SoCs. You will drive chip-level design decisions, own critical digital design blocks, and provide technical leadership across the SoC design team.
Job ResponsibilitiesDefine and own micro-architecture specifications for complex digital IP blocks and full SoC designsLead RTL design and implementation using Verilog and SystemVerilog, ensuring quality, reusability, and design closureDrive SoC integration — including IP assembly, interconnect architecture, clock and reset strategy, and power domain planningChampion AI adoption across digital design team — evaluating and integrating AI tools, establishing best practices, and driving team-wide productivity improvements through emerging AI workflowsCollaborate with verification, physical design, and firmware teams to ensure design intent is correctly implemented and validatedLead design reviews and provide technical direction to senior and junior design engineersDefine and enforce design guidelines, coding standards, and reuse methodologies across the team
Job RequirementsBachelor's degree or above in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related fieldPreferably 8+ years of ASIC/SoC digital design experienceProven ability to lead and mentor a team of design engineersDeep proficiency in RTL design using Verilog and SystemVerilogStrong understanding of SoC architecture — interconnects, memory subsystems, clock and power domainsProficiency in scripting languages such as Python, Perl, Shell, or TCLStrong interest in exploring and adopting AI tools to improve design productivity and engineering efficiency
