Job Responsibilities:
1. Responsible for module verification and system verification of SOC digital circuits;
2. Write verification specifications, test plans, and test cases according to the design specifications;
3. Set up the verification platform and environment; debug problems encountered in simulation to improve verification coverage and ensure verification completeness.
Job Requirements:
1. Experience in algorithm-based digital circuit development, with preference given to candidates with experience in PPA (power/performance/area) optimization, complex IP, or ultra-low power circuit design;
2. Proficient in Verilog or SystemVerilog syntax, and skilled in using scripting languages such as C/Tcl/Shell/Perl/Python;
3. Familiar with SDC constraint writing rules, familiar with Netlist ECO processes, proficient in using EDA tools such as VCS, Verdi, DC, Formality, and Spyglass, and understand the use of PT tools or UVM verification methods.
Job Responsibilities:
1. Define analog and mixed-signal circuit modules, and formulate technical specifications and detailed design schemes;2. Design, simulate, verify, and subsequently test analog and mixed-signal circuits;3. Guide layout planning and design.
Qualifications:
1. Prior experience working for a well-known overseas company is preferred;2. Solid foundation in analog circuits, proficient in the design of common analog circuits such as OPAMP/ADC/BGR/PLL/LDO, etc.;3. Proficient in the design of one or more high-speed interfaces (DDR/MIPI/Ethernet/PCIE/SATA, etc.);4. Experience in FinFET-based design and tape-out is a plus;5. Ability to work independently and a strong sense of teamwork.
Job Responsibilities:
1. Responsible for the customization and performance/yield analysis of advanced process devices;
2. Responsible for the extraction and modeling of advanced process parameters;
3. Job tasks include, but are not limited to, device performance analysis, test key design, process simulation, transistor-level circuit simulation, and yield data analysis.
Qualifications:
1. Recent PhD graduates or overseas PhD graduates within one year of graduation in fields including but not limited to Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, and Materials Science and Engineering;
2. Strong foundational knowledge of semiconductor device physics, integrated circuit design, and manufacturing;
3. Priority will be given to candidates with excellent familiarity with advanced process fabrication workflows and scripting skills;
4. Excellent academic performance, strong curiosity about new technologies and related professional fields, and strong learning and knowledge transfer abilities.
Responsibility1. Responsible for layout planning and design of analog and mixed-signal circuit modules; 2. Independently perform DRC, LVS, ERC, and other layout verification tasks; 3. Work closely with analog circuit design engineers to ensure effective communication and layout optimization; 4. Prepare and maintain relevant technical documentation.Requirement1. Bachelor’s degree or above, with relevant experience in IC layout design; 2. Proficient in Linux systems and skilled in using verification tools such as Cadence and Calibre; 3. Experience with 8nm or smaller process nodes is preferred; 4. Experience in SRAM layout design is a plus; 5. Strong communication and teamwork skills.
Responsibility1. Participate in chip product specification definition, including algorithm analysis and module-level specification development; 2. Implement and verify digital circuits at the RTL level, performing power, performance, and area (PPA) optimization; 3. Conduct digital circuit synthesis, timing analysis, and related design tasks.Requirement1. Experience in developing algorithm-based digital circuits; candidates with experience in PPA optimization, complex IP design, or ultra-low-power circuit design are preferred; 2. Proficient in Verilog or SystemVerilog, and skilled in using scripting languages such as C, Tcl, Shell, Perl, or Python; 3. Familiar with SDC constraint writing and Netlist ECO flows; proficient with EDA tools such as VCS, Verdi, DC, Formality, and SpyGlass; knowledge of PT tool usage or UVM verification methodology is a plus.
Responsibility1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3. Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement.Requirement1. Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes; 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage; 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred; 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++; 5. Familiar with 3D IC design; relevant experience is a plus; 6. Prior experience with STA signoff in tape-out projects is preferred.
